Integrated circuits such as those formed on single-crystal silicon substrates may typically include miniature capacitive structures integrated into the device circuitry. Each of these capacitive structures typically comprises a dielectric material sandwiched between bottom and top conductive electrodes. An integrated circuit such as a dynamic random access memory (DRAM) may contain millions of essentially identical capacitive structures, each of which functions as a charge storage device for one memory cell.
As the number of memory cells integrated in a circuit design increases, it is desirable to decrease the circuit surface area required for each capacitor, while maintaining sufficient capacitive charge storage capability to insure reliable operation. To this end, new dielectric materials have been sought with significantly higher dielectric constant than either silicon dioxide or silicon nitride. One class of these materials is the perovskite-phase metal oxides, typified by barium strontium titanate (BST) and lead zirconate titanate (PZT). Thin films of these materials may possess dielectric constants several orders of magnitude higher than conventional dielectrics. Many of these perovskite materials are also ferroelectric (they have the ability to at least semi-permanently alter crystal structure to retain an electric field polarization), making them attractive candidates for non-volatile ferroeletric random access memories.
A typical prior-art capacitor structure is shown in FIG. 1. This structure is formed on a semiconductor substrate 10 having an overlying field oxide 14 and a doped contact region 12. A polysilicon contact plug 16 provides electrical connection to contact region 12. A barrier layer 18 of a material such as TiN or TiAIN is interposed between platinum bottom electrode 20 and contact plug 16, to prevent downward diffusion of oxygen and upward diffulsion of silicon. A BST film 22 and a platinum top electrode 24 complete the capacitor structure. Although such a structure overcomes many BST-related problems, electrode oxidation and hillock formation problems remain because the bottom electrode structure is exposed to the high-temperature, strongly oxidizing environment commonly used for BST deposition. Also, the complex electrode structure of FIG. 1 requires multiple photolithography steps which degrade process margin for alignment-limited devices.